1. Field of the Invention
The present invention relates to a method and circuit for controlling an operation mode of a pseudo SRAM (PSRAM), a PSRM having the same, and a method for performing an operation mode thereof, and more particularly to, a method and circuit for controlling an operation mode of a PSRAM which can implement a mixed mode for simultaneously performing an asynchronous write operation and a synchronous write and synchronous read operation in a state where a synchronous mode is set by a mode register set, a PSRM having the same, and a method for performing an operation mode thereof.
2. Discussion of Related Art
In a semiconductor memory device, a random access memory (RAM) implements random access storage, and records and reads information. The RAM has been widely used for a computer or peripheral terminal apparatus. The RAM is advantageous in low price, small size, low power consumption, high speed call and nondestructive readout, but disadvantageous in that the whole stored data are deleted in power-off. The RAM is classified into a dynamic RAM (DRAM) in which information is prevented from being deleted by performing a refresh operation at an interval of a predetermined period in power-on, and a static RAM (SRAM) in which information is not deleted in power-on.
As explained above, a memory in which information is deleted in power-off is called a volatile memory, and a memory in which information is not deleted even in power-off, such as a read only memory (ROM) is called a nonvolatile memory. The SRAM is advantageous in access to an integrated circuit. However, if the SRAM has the same memory capacity as that of the DRAM, it requires elements three to four times as many as the DRAM. That is, the SRAM is more complicated and high-priced.
Accordingly, researches have been recently actively made on a PSRAM for implementing the operation of the SRAM by using a DRAM cell. As compared with the general SRAM, the PSRAM reduces a chip size and achieves high integration of 16 Mbit, 32 Mbit and 64 Mbit. However, the PSRAM has the same cell structure as that of the DRAM, and thus internally performs a refresh operation.
An operation mode for controlling the operation of the PSRAM is roughly divided into three, an asynchronous write and asynchronous read mode (asynchronous mode), an asynchronous write and synchronous read mode (mixed mode) and a synchronous write and synchronous read mode (synchronous mode). Such operation modes are selected by a mode register set. Once the operation mode is selected by the mode register set, the PSRAM is continuously operated in the selected operation mode. In order to operate the PSRAM in another operation mode, the operation mode is newly set by the mode register set. Here, the PSRAM is operated in the newly-set operation mode.
For the interface between the PSRAM and a NOR flash memory device, in a state where the synchronous mode is set, a synchronous write and synchronous read operation and an asynchronous write and synchronous read operation must be performed at the same time. However, when one of the three operation modes is selected by the mode register set, the asynchronous write and synchronous read operation and the synchronous write and synchronous read operation cannot be simultaneously performed.